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Super FinSim v9.0.2 Linux英文正式版(仿真環境軟體)
商品名稱： Super FinSim v9.0.2 Linux
商品分類： Linux系統專用軟體
商品類型： 仿真環境軟體
語系版本： 英文正式版
運行平台： LINUX (以官方網站為準)
更新日期： 2007-0三-1５
熱門標籤： 仿真環境軟體
FinSim
Super
破解說明:
Install.
Put license.dat in any directory of your choice.
Create an environment variable called "FINTRON_LICENSE_FILE"
and set its value to the location of license.dat
Enjoy!
內容說明:
Super-FinSim 仿真環境由一個附帶OVI的Virology編譯器，一個仿真構件和一個仿真內
核組成。Verilog編譯器用於（1）檢查設計的句法和語意的正確性，（2）依據設計申请
產生配置仿真內核所申请的代碼和數據。（三）選擇性的產生一個供另外應用程式處理的
中間花式表達。仿真構件用於鏈接構成一個仿真器所必要的部分文件，比如，編譯器的
輸出和仿真內核。主C鏈接器用於此目标。仿真內核是部分Veilog設計仿真公共代碼。一
旦配置完成，仿真內核就成為一個定制的Verilog設計的仿真器。Super-FinSim的仿真器
可以運行
Super-FinSim Verilog 編譯器有一個倏地和強大的能進行廣泛錯誤檢查和恢復的解析
器。别的，解析器能產生標明潛在設計錯誤的警告資訊代碼，比如，交換一個越界的數
組元素。
Super-FinSim Verilog 編譯器支援來自Verilog-XL的一些編譯器選項，包孕管教庫搜寻
坚守的選項。為便於援用下令文件同樣失去支援。必须事先指定希望的Super-FinSim 仿
真器模式，非论是編譯，解釋或編譯、解釋的混合狀態。假定不指定，Super-FinSim將
會試圖仿真編譯模式下的整個設計，假定發現了一個許可的編譯仿真器，否則，將在解
釋模式仿真設計。部分的編譯資訊儲存在登記文件『finvc.log』。
Super-FinSim仿真器操作仿真內核的波形例程介面支援實時波形顯示。最近的Super-
FinSim從數據I/O的工程捕捉系統（ECS）和Veribest』s Veriscope支援實時波形顯示。
用ECS波形顯示構造仿真器，必須指定選項『-ecs』。用Veriscope波形顯示構造仿真器
，必須指定選項『-veriscope』。
英文說明:
Super-FinSim is the top of the line FinSim Verilog simulator. Ever since
the first FinSim Verilog simulator has been sold in 199三, the FinSim
Verilog simulators have introduced many new features that have become
state of the art in Verilog simulation: mixed Compiled and Interpreted
simulation, simulation Farm that allows one engineer to manage hundreds
of simultaneous simulations, separate and incremental compilation, high
performance save and restart, direct integration with C code without the
need for PLI, etc.
Super FinSim supports the entire Verilog standard IEEE 1三6四-199５ and
many features of IEEE 1三6四-2001, which are listed under Support for
Verilog 2001. It's support includes SDF, VCD, PLI, as well as excellent
integration with other tools such as a tight integration via API (for
better performance than PLI integration) with Debussy and Verdi debug
environments from Novas Software, and excellent PLI integrations with
Specman from Verisity and Vera from Synopsys for test benches, MMAV from
Denali for memory models, Undertow from Veritools for debug environment,
HDLScore from Summit Design for code coverage, and others.
In the DA Solution Limited `96 benchmark, the predecessor of
Super-FinSim, FinSim-ECS, was rated the fastest Verilog simulator.
FinSim was rated the fastest PC-based Verilog simulator in the ASIC &
EDA benchmark.
相關商品:
Fintronic Super FinSim v10.0.0三 LINUX 英文正式版(FinSim Verilog仿真軟體)
Fintronic Super Finsim v9.2.9 LINUX 英文正式版(線性FinSim Verilog仿真器軟體)
Fintronic Super FinSim v9.三.8 LINUX 英文正式版(線性FinSim Verilog仿真器軟體)
Super FinSim v9.1.8 Linux 英文正式版(附帶OVI的Virology編譯器軟體)
Fintronic Super FinSim v10.0.0三 LINUX 英文正式版(FinSim Verilog 仿真軟體)
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